1. Field of the Invention
This invention is related to the Look-Up-Table (LUT) in Logic Element (LE), the basic building block for Field Programmable Gate array (FPGA). In particular, the configuration data for the Non-Volatile LUT (NV-LUT) of the invention are non-volatile in contrast to the conventional SRAM based volatile LUT. In comparison with the Complex Programmable Logic Device (CPLD) having separated on-chip non-volatile memory units for storing configuration data, the NV-LUT of the invention stores non-volatile configuration data in each LE unit for direct accessing in configurable digital circuitries.
2. Description of the Related Art
FPGA has been broadly applied for configuring digital circuitries. FPGA is more economical than ASIC (Application Specific Integrated Circuit) for digital circuit development especially in advanced technology nodes for their pricy mask set and process costs. The demands for higher logic gate counts and performance have been driving FPGA toward the advanced process technology nodes. The combination logic functions are configured with the SRAM-based LUTs in Logic Elements (LEs) in FPGA. Application specific functions of digital circuitries are accomplished by connecting the multiple configured LEs through interconnection matrixes in FPGA. Since the SRAM-based LUTs are volatile the configurations are lost after power off. The applications of FPGA are required to have non-volatile memory for storing non-volatile configuration data and to load back to the SRAM cells in the LUTs after turning on the FPGA chip. FPGA (low LE counts) integrated with on-chip non-volatile memory units is the CPLD. In contrast to the development of FPGA for large numbers of LEs processed with the state of art nano-meter CMOS technology, CPLD has stayed in low LE numbers for the sub-micron process technology. The main reason for CPLD lagging far behind the FPGA development is due to lack of cost effective and scalable non-volatile memory devices available for digital circuitries processed with the standard CMOS technology.
Furthermore since the conventional embedded NVM cells for storing configuration data used in CPLD are arranged in separated arrays fetching the configuration data requires sensing circuitry to convert NVM current signals into the digital signals and to write the converted digital signals into the SRAM cells in each LE. The data fetching and loading processes not only consume more chip power but also slow down the chip initialization speed. The requirements for NVM sensing circuitry and SRAM writing circuitry for non-volatile configuration data loading also economically hinder direct incorporating NVM devices in each LE unit. With the applications of complementary NVM devices (U.S. patent application Ser. Nos. 13/399,753 and 13/454,871, the disclosures of which are incorporated herein by reference in their entirety), a pair of complementary SGLNVM devices can store non-volatile digital data and direct output the digital signals without going through sensing amplifiers. Capable of outputting digital data signals direct from plural pairs of complementary SGLNVM devices storing non-volatile configuration data makes a fully integrated NV-LUT possible.
For the completion of the configurable digital circuitries, the configurable interconnection matrix using SGLNVM devices processed with standard CMOS logic process has been disclosed (U.S. patent application Ser. No. 13/683,721, the disclosure of which is incorporated herein by reference in its entirety).
In summary, we have demonstrated the new invention of NV-LUT using SGLNVM devices processed with standard CMOS logic process. Without adding process cost we have provided good solutions for configurable digital circuitries in the following aspects: 1) NV-LUT omits the requirement of non-volatile memory for non-volatile configuration data storage; 2) NV-LUT has faster circuit initialization speeds and less power consumption from the saving of external configuration loading; 3) NV-LUT is multiple-time configurable (proven 20 k-time configurations for the SGLVNM devices fabricated by a foundry); 4) NV-LUT is scalable according to the standard logic process technology nodes. The NV-LUT of the invention can meet the demands for high logic gate counts and high performance in configurable digital circuitries from the benefits of the advanced logic process technology.